Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask may contain a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g., comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus, commonly referred to as a step-and-scan apparatus, each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction. Since, in general, the projection system will have a magnification factor M (generally <1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic devices as described herein can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g., an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc.
For the sake of simplicity, the projection system may hereinafter be referred to as the “lens;” however, this term should be broadly interpreted as encompassing various types of projection systems, including refractive optics, reflective optics, and catadioptric systems, for example. The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, and such components may also be referred to below, collectively or singularly, as a “lens.” Further, the lithographic apparatus may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic apparatus are described, for example, in U.S. Pat. No. 5,969,441, incorporated herein by reference.
The photolithographic masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. The design rule limitations are typically referred to as “critical dimensions” (CD). A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit.
With the rapid downsizing of feature dimensions in semiconductor manufacturing, the IC industry has demanded exposure tools to be capable of printing device features having a pitch of one-half of the exposure wavelength. For example, for a ArF (193 nm) exposure, the desired feature pitch is below 100 nm. As is known, the printing resolution definition is:minimum half-pitch of critical features=k1(λ/NA)where, k1 is the process capability                λ is exposure wavelengths        NA is numerical aperture of the lensThe theoretical printing resolution limit is at k1=0.25. This means that, at this k1 level, there is no imaging contrast for such pitch features. For example, using today's state-of-the-art ArF exposure tools with NA=0.93, the minimum pitch can be printed is 100 nm or above. In reality, in order to obtain a reasonable process window, the k1 needs to be slightly above 0.27. This pushes up the minimum feature pitch to be at least greater than 108 nm. In order to print feature pitch below 108 nm, it is necessary to use shorter exposure wavelengths or higher NA, either of which can be quite an expensive capital equipment proposition and not feasible for a near term solution.        
However, there are known techniques that allow for a reduction in the minimum CD that can be imaged or reproduced in a wafer. One such technique is the double exposure technique wherein features in the target pattern are imaged in two separate exposures. For example, one commonly known double exposure technique is dipole illumination. In this technique, during a first exposure the vertical edges of the target pattern (i.e., features) are illuminated and then during a second exposure the horizontal edges of the target pattern are illuminated. As noted, by utilizing two exposures, improved imaging performance may be obtained.
Another known double exposure technique allows the features of a given target pattern to be separated into two different masks and then imaged separately to form the desired pattern. Such a technique is typically utilized when the target features are spaced so closely together that it is not possible to image the individual features. In such a situation, for each exposure mask, the original pitch features are “decomposed” and separately placed into two exposure masks. For each mask, the feature pitch ranges increase and the k1 becomes much higher. The imaging for each exposure mask can then be more readily achievable with a less resolution demanding process. Such a process is illustrated in FIGS. 1a-1d. It is noted that this technique is also known as “coloring”.
Referring to FIGS. 1a-1d, FIG. 1a illustrates a set of densely spaced features 12 having a pitch dimension which is too small to properly imaging the features using a single exposure. In order to decompose such a pattern, the features are alternately assigned one of two colors as shown in FIG. 1b so as to create a first set of features 14 and a second set of features 16. The first set of features 14 are then placed into a first exposure mask (as shown in FIG. 1c) and the second set of features 16 are placed into a separate second exposure mask (as shown in FIG. 1d). As can be seen, the features in both the first exposure mask and the second exposure mask exhibit a pitch which is greater than the pitch between the features in the original target pattern. The two exposure patterns are then imaged separately to create the desired target pattern shown in FIG. 1a. 
FIGS. 2a-2e illustrate an exemplary two-exposure process for the exposure masks illustrated in FIGS. 1c and 1d. Referring to FIG. 2a, the first step of the two exposure process is to expose the first exposure mask to as to define resist patterns corresponding to the first set of features 14, and then the resist patterns are hardened (FIG. 2b). Next, resist is reapplied (FIG. 2c) and then the second exposure mask is exposed so as to form resist patterns corresponding to the second set of features 16 adjacent the first set of assist features 14. The result of the process is illustrated in FIG. 2e, which is a pattern corresponding to the densely spaced features illustrated in FIG. 1a. 
While feature pitch decomposition for 1-dimensional features, such as illustrated in FIGS. 1a-1d, is generally well known by the lithography-engineering field, currently there is no known systematic process or methodology regarding how to decompose or “color” target patterns including complex and random 2D features. It is an object of the present invention to provide a systematic approach and method for coloring target patterns including complex 2-dimensional features and patterns.